Introduction
In information technology, hardware is the physical aspect of computers, network devices and others. The term is a way to distinguish the “box” and the electronic circuitry and components of a computer/network device from the program you put in it to make it do things. The program came to be known as the software.
Software or programming can easily be varied. You can put an entirely new program in the hardware and make it create an entirely new experience for the user. You can, however, change the modular configurations that most computers come with by adding new adapters or cards that extend the computer’s capabilities. Hardware being a collective term, includes computers and its peripheral devices, cables, power devices, display devices, telecom equipment to name a few.
Basics
Components
Let’s make sure that we know the markings for all the types of resistors, capacitors, ICs, and everything else required to know.
Resistors
Through Hole Resistors
Standard resistors are NOT polarized and can be placed in the PCB either way round.The most common have four bands. Bands 1 and 2 identify the first two digits, band 3 is the Multiplier and band 4 is the tolerance (normally Gold 5%). The through hole technology refers to the use of leads on the components that are inserted into holes drilled in printed circuit boards (PCB) and soldered to pads on the opposite side.
Resistor Colour Codes
SMD Resistors
SMD resistors or Surface Mount Device resistors are rectangular in shape. These chip resistors [Fig:
] have metallised areas at either end of the body and this enables them to make contact with the printed circuit board through the solder. A three figure SMD resistor coding system is the one that is normally used. The first two figures in the code indicate the significant figures, and the third is a multiplier. This is the same as the coloured rings used for wired resistors, except that actual numbers are used instead of colours.
When resistance value falls below ten ohms, the letter “R” is used to indicate the position of the decimal point. Also a four digit marking is used for high tolerance resistors.
Capacitors
Electrolytic Capacitors
Electrolytic capacitors are polarized devices which means they must be inserted with the correct polarity. Electrolytic have one lead longer than the other and this denotes the POSITIVE lead and on the opposite side of body is a black band with a minus sign.
Ceramic Capacitors
Ceramic Capacitors are non-polar device, that means they do no have polarities. So we can connect it in any direction on a circuit board.
Surface Mount Ceramic Capacitors
Surface-mount components like MLCCs(Multi Layer Ceramic Capacitors) are non-polar and are cheaper (because they have no leads) and a little bit smaller than their counterparts with leads, and they need no holes in the PCB, a second reduction of costs. They are designed to be handled by machines rather than by humans, to reduce costs.
Capacitor codes and markings
ICs
Programmable Logic Device
A PLD, or programmable logic device, is an electronic component that is used in order to build digital circuits that are reprogrammable. The PLD types are Complex Programmable Logic Device(CPLD), Field Programmable Gate Array(FPGA) etc., which you will be able to choose based on their technical attributes and your search results will be narrowed to match your specific programmable logic device application complexity needs. There are a lot of manufacturers like Xilinx, Altera, Lattice, Atmel etc., who have a range of surface mount or through hole ICs to choose from with their own specific markings.
Platform Flash PROM
The in-system programmable configuration Programmable ROMs are basically used in combination with FPGA. Unlike CPLDs which are EEPROM based, FPGAs lose their configuration on power reboot, hence an additional flash memory would be required on board to configure it each time on power up. There are many Flash ROMs available and usually the PLD manufacturers release their own PROMs with specific marking which represents different memory capacities.
PSoC Mixed Signal Array
PSoC is an FPGA that includes programmable analog capabilities as well. They are generally expensive and are largely limited to fairly narrow application domains where the use of external analog components is undesirable from either a board space or power consumption perspective.PSoC devices include a fast CPU, Flash program memory, SRAM data memory, and configurable blocks of analog, digital logic and IO are included in a range of convenient pinouts and packages.
Integrated Circuit (Through Hole/SMD)
Oscillators
Most electronic circuitry uses the oscillator when there is a requirement of clock signal. This includes the FPGA board as well.The oscillators come in 4 pins package and contain the electronic required to oscillate, so that an oscillator generates a clock by itself when it is powered-up.They are selected based on the circuit clock frequency requirement like 25MHz, 50MHz etc.The metal case of canned oscillators is connected to ground and provides shielding.
Transceivers
The Transceiver(Eg:RS232) is a hardware layer protocol converter IC. Commonly known as a RS-232 Transceiver, it consists of a pair of drivers and a pair of receivers. At a very basic level, the driver converts TTL or CMOS voltage levels of the circuitry to TIA/EIA-232-E levels, which are compatible for serial port communications. The receiver performs the reverse conversion.
Buffer/Driver
Buffer ICs with open-collector outputs form the basis of a number of clever tricks for level-shifting and interfacing between different types of logic(TTL/CMOS), and from logic to other types of electronic circuits. So, where with most digital electronics, the output of a buffer (or other logic gate) is a “high” or “low” voltage, an open collector has two different states: Output transistor disabled or output transistor enabled.This, therefore, is a neat way to build a logic-level shifter where the output when disabled can be pulled up to any desired voltage like 3.3V, 5V, 12V etc.
Other Components
There are various other components which may be required for building a circuit. Some of which are shown in the figure below.
Other Components(Through Hole/SMD)
I/O Ports
I/O stands for Input and Output. In computing, input/output or I/O is the communication between an information processing system (such as a computer) and the outside world, possibly a human or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it. A few of the I/O ports are as follows;
RS232
Despite the development of newer digital interface standards, the humble RS-232 serial port is still a very popular means of data transfer. It is also called “EIA-232”. The purpose and timing of the signal lines and the connectors are to be defined (D-sub 25-pin or D-sub 9-pin). RS-232C is a short distance(15m), full duplex, 1:1 connection standard. Check the below figure for the details on pin signal assignments.
RS232 pin layout and connection
PCI-X
Stands for “Peripheral Component Interconnect Extended.” Once again, “Ex” is abbreviated with an “X” instead of an “E.” Most desktop computers include one or more PCI slots for expanding the computer’s I/O capabilities. Common PCI cards include network cards, sound cards, and video cards. PCI-X cards are available at speeds of 66MHz,133MHz & 533MHz compared to the earlier PCI which supported only 66MHz data speed.PCI-X cards can only be installed in PCI-X slots, but the slots themselves are backwards compatible with PCI cards.Going forward, PCIe ,i.e, PCI express, the high-speed serial computer expansion bus standard, is expected to replace PCI & PCI-X standards.
JTAG
Joint Test Action Group, also known as JTAG, is the common name for IEEE std 1149.1. This standard defines a particular method for testing board-level interconnects, which is also called Boundary Scan. In short, JTAG was created as a way to test for common problems, but lately has become a way of configuring devices. FPGA manufacturers allow configuring the FPGA through JTAG connector, and use the JTAG signals inside the FPGA core.
Other Ports
There are so many different ways to interface to TVs, Computers, monitors and other electronic devices these days — and it can get confusing, especially because so many of these ports and connectors have become obsolete over the years. The ones which can still be seen are USB, HDMI, DVI, Display Port, VGA to name a few.
Test Equipments
DC Power Supply
As the name says, DC power supply provides the DC voltage to power the circuit. The advantage of using a programmable power supply is that it can cater to circuits with varying ranges of voltages and current requirements.
Signal/Function generator
A function generator is usually a piece of electronic test equipment or software used to generate different types of electrical waveforms over a wide range of frequencies.They are used in the development, test and repair of electronic equipment.Some of the most common waveforms produced by the function generator are the sine wave , square wave, triangular wave and sawtooth shapes.Another feature included on many function generators is the ability to add a DC offset.
Multi-meter
A multimeter or a multitester is an electronic measuring tool that is a combination of several tools in one unit. It usually includes an ammeter, voltmeter, and ohmmeter. Digital multimeters are sometimes called DMM too. Often they include a number of additional specialized features or advanced options. Technicians with specific needs, therefore, can seek out a model targeted for particular tasks.
Test Equipments
CRO
An oscilloscope or Cathode Ray Oscilloscope, is a type of electronic test instrument that allows observation of varying signal voltages, usually as a two-dimensional plot of one or more signals as a function of time. Oscilloscopes are used to observe the change of an electrical signal over time, such that voltage and time describe a shape which is continuously graphed against a calibrated scale. The observed waveform can be analyzed for such properties as amplitude, frequency, rise time, time interval, distortion and others. However, oscilloscopes are somewhat limited with only two or four input channels to correlate a small number of digital, analog and serial signals.
Logic Analyzers
A logic analyzer is an electronic instrument that captures and displays multiple signals(>34 channels) from a digital system or a complex digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, assembly language, or may correlate assembly with source-level software. Logic Analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system.
Board build
Design Schematics
Circuit diagrams are designed based on specifications and entered using an easy to use schematic editor like Design works. Component symbols chosen from the component bar are positioned, moved, rotated and/or mirrored on the screen by the mouse.You can open any number of circuit files or sub-circuits, cut, copy and paste circuit segments from one circuit into another, and, of course analyze any of the currently open circuits using waveforms.
Part of a Schematic (Circuit editor window in red frame)
Apart from the schematic data, the schematic editor can be used to generate bill of material list and the netlist. The netlist file(mostly) or schematic file(some cases) can be used as an input to the PCB layout generation tool depending on the requirements.
BOM & Netlist
PCB layout to the Final Board
PCB layers are the determining factor in the power and capacity of a printed circuit board. People often wonder whether a one-layer PCB will suffice, or if it is better to go with a two- or four-layer PCB.The number of layers largely depend on your budget and functional needs in a PCB.Anything more than 2 layers is referred to as a multilayered board.
The layout or the film diagram(4 layers) of the circuit as shown in the below figure will be generated by the design bureau which needs to be checked before giving a go ahead to the board generation.The visual continuity check can done by taking the netlist as a reference and would be required since the netlist might have been modified by the vendor due to compatibility issues with their PCB film generation tool.
PCB Layers Layout
Making sure your schematic is correct and when you are done with the layout check, it is time to get your PCB design ready for manufacturing. So, once your PCB returns from the manufacturing with the components mounted , it looks like the one shown in the figure below(part of a board). You wanna make sure you do the necessary steps for a good board bring-up. Failing to do it would result in a dead or fried board. Or it could be worse – a board that looks like it works, but actually has hidden hardware issues that only crop up later when developing firmware/software, which are very difficult to debug.
Final Board
The first check you want to do is continuity testing. This might be daunting because there are many pads on an average PCB and checking each of the connection with a multimeter would be cumbersome. It will be over quicker than you’d think, and it’s very worth your time to catch issues early on like a pad isn’t connected to a desired power rail, or that two power rails are shorted to each other etc. The second check you want to do is a visual inspection. If you have small parts on your PCB, this is much easier with a magnifying glass. This inspection would detect issues like un-drilled vias and through holes, shorted pads and traces etc.
After you’ve done as many checks as you can, take a deep breath and power it on using the programmable power supply with the required voltage and current. If you have done your checks properly you should be confident of the board powering up without any issues.
Implementing PLD designs
Before starting with the CPLD/FPGA coding, we need to create a design document based on which can start coding.The design document should detail on the low level FPGA/CPLD architecture which should contain the description of functionalities of each of the modules, pin details, internal architecture, implementation details and timing analysis of the block as a whole.Let us consider implementing a simple UART with only the receiver functionality, the block diagram of which is shown as below;
Block Diagram
Description & Coding
A UART is one of the simplest methods of talking to your FPGA. It can be used to send commands from a computer to an FPGA(here) and vice versa. A UART is an asynchronous interface.In any asynchronous interface, the first thing you need to know is when in time you should sample (look at) the data. If you do not sample the data at the right time, you might see the wrong data. In order to receive your data correctly, the transmitter and receiver must agree on the baud rate. The baud rate is the rate at which the data is transmitted.
The FPGA is continuously sampling the serial data input line. Once it sees the line transition from high to low, it knows that a UART data word is coming. This first transition indicates the start bit. Once the beginning of the start bit is found, the FPGA waits for one half of a bit period. This ensures that the middle of the data bit gets sampled. From then on, the FPGA just needs to wait one bit period (as specified by the baud rate) and sample the rest of the data. The FSM below depicts the whole cycle of operations.
UART Receiver State Machine
VHDL Implementation
-- This file contains the UART Receiver. This receiver is able to
-- receive 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When receive is complete o_rx_dv will be
-- driven high for one clock cycle.
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- Example: 16.9344 MHz Clock, 2400 baud UART
-- (16934400)/(2400) = 7056 Clocks per bit
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity UART_RX is
generic (
g_CLKS_PER_BIT : integer := 7056 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_RX_Serial : in std_logic;
RST_L : in std_logic;
o_RX_DV : out std_logic;
o_RX_Byte : out std_logic_vector(7 downto 0)
);
end UART_RX;
architecture rtl of UART_RX is
type t_SM_Main is (s_Idle, s_RX_Start_Bit, s_RX_Data_Bits,
s_RX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_RX_Data_R : std_logic := '0';
signal r_RX_Data : std_logic := '0';
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_RX_Byte : std_logic_vector(7 downto 0) := (others => '0');
signal r_RX_DV : std_logic := '0';
begin
-- Purpose: Double-register the incoming data.
-- This allows it to be used in the UART RX Clock Domain.
-- (It removes problems caused by metastabiliy)
p_SAMPLE : process (i_Clk, RST_L)
begin
if RST_L = '0' then
r_RX_DV <= '0';
r_Clk_Count <= 0;
r_RX_Byte <= (others => '0');
elsif rising_edge(i_Clk) then
r_RX_Data_R <= i_RX_Serial;
r_RX_Data <= r_RX_Data_R;
end if;
end process p_SAMPLE;
-- Purpose: Control RX state machine
p_UART_RX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
r_RX_DV <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if r_RX_Data = '0' then -- Start bit detected
r_SM_Main <= s_RX_Start_Bit;
else
r_SM_Main <= s_Idle;
end if;
-- Check middle of start bit to make sure it's still low
when s_RX_Start_Bit =>
if r_Clk_Count = (g_CLKS_PER_BIT-1)/2 then
if r_RX_Data = '0' then
r_Clk_Count <= 0; -- reset counter since we found the middle
r_SM_Main <= s_RX_Data_Bits;
else
r_SM_Main <= s_Idle;
end if;
else
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Start_Bit;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles to sample serial data
when s_RX_Data_Bits =>
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Data_Bits;
else
r_Clk_Count <= 0;
r_RX_Byte(r_Bit_Index) <= r_RX_Data;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_Data_Bits;
else
r_Bit_Index <= 0;
r_SM_Main <= s_RX_Stop_Bit;
end if;
end if;
-- Receive Stop bit. Stop bit = 1
when s_RX_Stop_Bit =>
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Stop_Bit;
else
r_RX_DV <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
r_SM_Main <= s_Idle;
r_RX_DV <= '0';
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_RX;
o_RX_DV <= r_RX_DV;
o_RX_Byte <= r_RX_Byte;
end rtl;
The code above uses one Start Bit, one Stop Bit, eight Data Bits, and no parity half-duplex communication. The IDE for either the Altera or Xilinx device enables analysis and synthesis of HDL designs, which makes the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design’s reaction to different stimuli, and configure the target device with the programmer. .
Functional Simulation
If you want to simulate your code (and you should) you need to use a testbench. The testbench below tests the above Receiver code. It is programmed to work at 2400 baud. Note that this test bench is for simulation only and cannot be synthesized into functional FPGA code. Scripting language like the Tcl/tk can be used to run the verification environment which consists of the source code, test bench and any other additional modules. ModelSim simulator is one of the most reliable simulators used by many to verify their complex VHDL/Verilog code designs.
VHDL Testbench
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity uart_tb is
end uart_tb;
architecture behave of uart_tb is
component uart_rx is
generic (
g_CLKS_PER_BIT : integer := 7056 -- Needs to be set correctly
);
port (
i_clk : in std_logic;
rst_l : in std_logic;
i_rx_serial : in std_logic;
o_rx_dv : out std_logic;
o_rx_byte : out std_logic_vector(7 downto 0)
);
end component uart_rx;
-- Test Bench uses a 16.9344 MHz Clock
-- Want to interface to 2400 baud UART
-- 16934400 / 2400 = 7056 Clocks Per Bit.
constant c_CLKS_PER_BIT : integer := 7056;
constant c_BIT_PERIOD : time := 417 us;
signal r_CLOCK : std_logic := '0';
signal r_RST : std_logic;
signal w_RX_DV : std_logic;
signal w_RX_BYTE : std_logic_vector(7 downto 0);
signal r_RX_SERIAL : std_logic := '1';
-- Low-level byte-write
procedure UART_WRITE_BYTE (
i_data_in : in std_logic_vector(7 downto 0);
signal o_serial : out std_logic) is
begin
-- Send Start Bit
o_serial <= '0';
wait for c_BIT_PERIOD;
-- Send Data Byte
for ii in 0 to 7 loop
o_serial <= i_data_in(ii);
wait for c_BIT_PERIOD;
end loop; -- ii
-- Send Stop Bit
o_serial <= '1';
wait for c_BIT_PERIOD;
end UART_WRITE_BYTE;
begin
-- Instantiate UART Receiver
UART_RX_INST : uart_rx
generic map (
g_CLKS_PER_BIT => c_CLKS_PER_BIT
)
port map (
i_clk => r_CLOCK,
rst_l => r_RST,
i_rx_serial => r_RX_SERIAL,
o_rx_dv => w_RX_DV,
o_rx_byte => w_RX_BYTE
);
r_CLOCK <= not r_CLOCK after 50 ns;
r_RST <= '1';
process is
begin
-- Send a command/data to the UART
wait until rising_edge(r_CLOCK);
UART_WRITE_BYTE(X"69", r_RX_SERIAL);
wait until rising_edge(r_CLOCK);
-- Check that the correct command/data was received
if w_RX_BYTE = X"69" then
report "Test Passed - Correct Byte Received" severity note;
else
report "Test Failed - Incorrect Byte Received" severity note;
end if;
assert false report "Tests Complete" severity failure;
end process;
end behave;
Through the test bench code we are writing the data “0x69” and reading it which verifies the functionality of the UART receiver design. Also the o_RX_DV signal should be observed to go high once the stop bit is read.
UART receiver receiving 0x69
Synthesis, Place & Route
Analysis stage of Analysis & Synthesis examines the logical completeness and consistency of the project, and checks for boundary connectivity and syntax errors. Analysis & Synthesis also synthesizes and performs technology mapping on the logic in the design entity or project’s files. It infers flip flops, latches, and state machines from Verilog HDL and VHDL. It creates state assignments for state machines and makes choices that minimize resources usage. It also uses algorithms to minimize gate count, remove redundant logic, and use the device architecture (e.g. DSP blocks and memory blocks) as efficiently as possible.
The Place & Route tool will do an optimal job at implementing timing specifications. It automatically assigns each logic function to the best logic cell location for routing and timing, and selects appropriate interconnection paths and pin assignments. However this will not be the case in challenging designs.If user have a very good idea about the design then user can find a good way to place different components of design using floor planner manually or fine tune already placed design. For example you can place your DDR logic nearby to DDR pins or take advantage of using clock tree etc. Also, many things can pop out when visually inspecting critical paths and component placements, which will not be obvious when looking at text-based reports and summaries.
Programming the Device & Testing on PCB
Once you have successfully compiled and simulated a project with the Altera Quartus/Xilinx ISE software, you can program the respective device with the configuration file(*.pof/*.sof) and test it in the target circuit. The software includes interfaces to the Altera Programming Unit (APU). The APU provides the hardware and software needed for programming Altera devices, when used with the appropriate programming adapters. Altera programming software can also be used with download cables such as USB-BlasterTM, ByteBlasterTM II, ByteBlasterMVTM or MasterBlasterTM cables.
Configuring Altera Device
Once the device is successfully programmed, the board as a whole can be tested for serial communication with a terminal. Here the test equipments like multimeter, oscilloscope etc., can be used as and when required in order to make the board work as per the requirements.
Credits:
Knowledge, Experience, Datasheets
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